1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing such a semiconductor device, and more particularly to a semiconductor device having an increased effective mount area percentage which represents a ratio between the chip area of the semiconductor device and the area in which the semiconductor device is mounted on a packaging board such as a printed-circuit board or the like, and a method of manufacturing such a semiconductor device.
2. Description of the Prior Art
Generally, a semiconductor device comprising a transistor element fabricated on a silicon substrate is mainly of a structure as shown in FIG. 1A of the accompanying drawings. As shown in FIG. 1A, a semiconductor device comprises a silicon substrate 1, an island 2 such as a heat-radiating plate or the like on which the silicon substrate 1 is mounted, lead terminals 3, and a molded resin body 4 by which the silicon substrate 1, the island 2, and the lead terminals 3 are encased.
The silicon substrate 1 is fixed to the island 2, which is made of a copper-based material, by a joining material 5 such as a soldering material. A semiconductor element formed on the silicon substrate 1 has base and emitter electrodes electrically connected to the lead terminals 3 by wires 6 according to a wire bonding process. The semiconductor element has a collector electrode electrically connected to a lead terminal that is integral with the island 2. After the silicon substrate 1 is mounted on the island 2 and the semiconductor element is electrically connected to the lead terminals, the assembly is encased by the molded resin body 4, which is made of a thermosetting resin such as an epoxy resin or the like, according to a transfer molding process, thereby producing a three-terminal semiconductor device in which the silicon substrate 1 and portions of the lead terminals 3 are fully covered with the molded resin body 4.
As shown in FIG. 1B of the accompanying drawings, the transfer molding process is carried out by a molding assembly including upper and lower molds 7, 8 which jointly define a mold cavity 9. A lead frame 10 on which the silicon substrate 1 and the wires 6 are mounted by die bonding and wire bonding is placed in the mold cavity 9, and then the thermosetting resin is introduced into the mold cavity 9.
The molded semiconductor device is usually mounted on a packaging board such as a glass epoxy board or the like, and electrically connected to other semiconductor devices and circuit elements on the packaging board. The semiconductor device thus connected will operate as a component in an electronic circuit.
FIG. 2 of the accompanying drawings shows a semiconductor device mounted on a packaging board. As shown in FIG. 2, a semiconductor device 20 is mounted on a packaging board 30 and has base and emitter electrodes connected to lead terminals 21, 23 and a collector terminal connected to a lead terminal 22.
The semiconductor device 20 is mounted on the packaging board 30 in amount area thereon which is defined as a region surrounded by the lead terminals 21, 22, 23 and electrically conductive pads connected to the lead terminals 21, 22, 23. The mount area is much larger than the area of the silicon substrate (semiconductor chip) in the semiconductor device 20. Most of the mount area is taken up by the molded resin body of the semiconductor device 20 and the lead terminals 21, 22, 23.
A ratio between the area of the semiconductor chip which performs functions of the semiconductor device 20 and the mount area is referred to as an effective area percentage. It has been confirmed that the effective area percentage of resin-molded semiconductor devices is very small. The small effective area percentage means that most of the mount area is a dead space not directly related to the semiconductor chip, and also means that there is a large dead space on the packaging board 30 on which the semiconductor device 20 is connected to the other semiconductor devices and circuit elements. The large dead space poses limitations on efforts to achieve a higher density on the packaging board 30 and make the packaging board 30 smaller in size.
Such problems manifest themselves particularly with semiconductor devices having small package sizes. For example, a semiconductor chip installed in the contour type SC-75A according to the EIAJ standards has a maximum size of 0.40 mm×0.40 mm as shown in FIG. 3 of the accompanying drawings. When the semiconductor chip is connected to metal lead terminals by wires and encased by a molded body, the overall size of the resultant semiconductor device has a size of 1.6 mm×1.6 mm. The chip area of the semiconductor device is 0.16 mm2, and the mount area in which the semiconductor device is mounted is 2.56 mm2, assuming that it is substantially the same as the area of the semiconductor device. Consequently, the effective area percentage of the semiconductor device is about 6.25%. Therefore, most of the mount area is a dead space not directly related to the area of the semiconductor chip.
The above problems with respect to the effective area percentage are serious if the semiconductor device has a small package size, as described above, and a large chip size. The same problems also occur with respect to resin-molded semiconductor devices in which semiconductor chips are connected to metal lead terminals and encased by molded resin bodies.
Recent electronic devices including portable information processing devices such as personal computers, electronic notepads, etc., 8-mm video cameras, portable telephone sets, cameras, liquid-crystal television sets, etc. have packaging boards which tend to be higher in density and smaller in size as the electronic devices themselves become smaller in size.
As described above, the large dead space contained in the mount area for resin-molded semiconductor devices has posed limitations on the efforts to reduce the size of packaging boards, and hence has prevented packaging boards from being reduced in size.
One conventional proposal for increasing the effective area percentage is disclosed in Japanese laid-open patent publication No. 3-248551. The disclosed arrangement will be described below with reference to FIG. 4 of the accompanying drawings. According to the disclosure, in order to minimize the mount area in which a resin-molded semiconductor device is mounted on a packaging board or the like, lead terminals 41, 42, 43 to which base, emitter, and collector terminals of a semiconductor chip 40 are connected do not project outwardly from sides of a molded resin body 44, but are bent along the sides of the molded resin body 44.
Inasmuch as the distal ends of the lead terminals 41, 42, 43 do not project outwardly, the mount area of the resin-molded semiconductor device is reduced by an area which would otherwise be taken up by the projecting ends of the lead terminals 41, 42, 43, resulting in a slight increase in the effective area percentage.
The distal ends of the lead terminals 41, 42, 43 are bent around corners of the lower surface of the molded resin body 44. Because the lead terminals 41, 42, 43 are required to withstand stresses imposed when they are bent, the lead terminals 41, 42, 43 need to have a sufficiently large length embedded in the molded resin body 44. As a consequence, the size of the molded resin body 44 is much larger than the size of the semiconductor chip 40, and hence the effective area percentage may not substantially be reduced. The lead terminals 41, 42, 43 required to be connected to the semiconductor chip 40 increase the cost of materials used and complicate the fabrication process, with the result the manufacturing cost cannot be lowered.
To maximize the effective area percentage, a semiconductor chip may directly be mounted on a packaging board for equalizing the area of the semiconductor chip and the mount area substantially to each other.
Japanese laid-open patent publication No. 6-338504 discloses a conventional process of mounting a semiconductor chip directly on a board such as a packaging board. According to the disclosed process, as shown in FIG. 5 of the accompanying drawings, a flip chip comprising a plurality of bump electrodes 46 formed on a semiconductor chip 45 is bonded to a packaging board 47 by a face-down bonding process. The disclosed process is used primarily with respect to horizontal semiconductor devices such as MOSFETs or the like in which gate (base), source (emitter), and drain (collector) electrodes are formed on one principal surface of a silicon substrate, with current or voltage paths extending horizontally.
The flip-chip mounting, however, cannot be applied to vertical semiconductor devices such as transistor devices or the like in which a silicon substrate serves as an electrode and electrodes are formed on different surfaces, with current paths extending vertically.
Another conventional process of mounting a semiconductor chip directly on a board such as a packaging board is revealed in Japanese laid-open patent publication No. 7-38334, for example. According to the revealed process, as shown in FIG. 6 of the accompanying drawings, a semiconductor chip 53 is mounted on an electrically conductive pattern 52 on a packaging board 51 by a die bonding process, and the electrically conductive pattern 52 around the semiconductor chip 53 is electrically connected to the semiconductor chip 53 by wires 54. The disclosed process can be applied to semiconductor chips such as vertical transistors in which a silicon substrate serves as an electrode.
The wires 54 which connect the semiconductor chip 53 to the electrically conductive pattern 52 disposed therearound are usually in the form of thin gold wires.
In order to increase the peel strength (tensile strength) of bonding areas which are bonded to the thin gold wires, the wires 54 should preferably be bonded in a heating atmosphere in the range of about 200° C. to 300° C. When a semiconductor chip is mounted on a packaging board made of insulating resin by a die bonding process, however, if the assembly is heated to the above temperature range, then the packaging board will be distorted, and the soldering material with which other circuit elements including chip capacitors, chip resistors, etc. mounted on the packaging board will be melted. To avoid such difficulties, it has been customary to mount a semiconductor chip on a packaging board made of insulating resin according to a die bonding process at a temperature ranging from about 100° C. to 150° C. Such a low temperature range tends to reduce the peel strength of the bonding areas.
Since the die-bonded semiconductor chip is covered and protected by the encasing resin such as an epoxy resin or the like, the reduction in the peel strength allows bonded regions to be peeled off due to shrinkage of the epoxy resin upon thermosetting.
The lead frame 10 and the mold cavity 9 (see FIG. 1B) can be positioned relatively to each other with an accuracy limit of ±50μ. Therefore, the size of the island 2 (see FIG. 1A) should be designed in view of the above positional accuracy limit. The positional accuracy limit reduces the dimensions of the island 2 with respect to the outer dimensions of the package, resulting in limitations on the maximum dimensions of the semiconductor chip 1 that can be accommodated in the package.